LDPC解码器功耗优化

M. Zinchenko, A. M. Levadniy, Y. A. Grebenko
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引用次数: 2

摘要

本文介绍了一种用于现场可编程门阵列的DVB-S2标准低密度奇偶校验码解码器体系结构的开发结果。它支持标准附录中描述的几种码率和码字长度。所提出的解码器架构具有部分并行结构,可以实现高解码性能和有效利用芯片面积。证实了奇偶校验矩阵结构中存在双对角子矩阵,并给出了一种消除双对角子矩阵的方法。在工作中,分析了影响现场可编程门阵列静态和动态功耗的参数。在此基础上,提出了降低能耗的算法和架构方法。本文介绍了降低芯片功耗的开发架构和方法。
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LDPC Decoder Power Consumption Optimization
The paper presents the results of developing a decoder architecture of low-density parity check code of the DVB-S2 standard for field programmable gate array. It supports several code rates and codeword lengths described in the appendix of the standard. The proposed decoder architecture has a partially parallel structure, which allows to achieve high decoding performance and efficient use of chip area. The presence of double-diagonal submatrices in the structure of the parity check matrices was also confirmed, and a method for eliminating them was implemented. In the work, an analysis of parameters affecting the static and dynamic power consumption in the field programmable gate array was made. Based on it, algorithmic and architectural methods for reducing consumption are proposed. The paper describes the developed architectures and methods to reduce chip power consumption.
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