HexCell: fpga上可进化收缩阵列的六边形单元(摘要)

F. Hussein, Luka Daoud, N. Rafla
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引用次数: 2

摘要

本文提出了一种新的可进化收缩阵列细胞结构。HexCell是一个六角形的可平铺处理单元,可以在现场可编程门阵列(fpga)上实现和动态重新配置。该单元包含一个功能单元、三个输入端口和三个输出端口。它支持两种并发配置方案:动态部分重新配置(DPR),其中功能单元在运行时部分重新配置,以及虚拟重新配置电路(VRC),其中单元输出端口绕过其中一个输入数据或选择功能单元输出。因此,HexCell结合了DPR和VRC的优点,包括资源感知、重新配置速度和路由灵活性。此外,单元结构支持流水线和数据同步,以实现图像处理等数据密集型应用程序的高吞吐量。HexCell由二进制字符串(染色体)表示,该字符串编码单元格的功能和输出选择。与最先进的收缩阵列相比,我们开发的可进化的HexCell阵列支持更多的输入和输出,各种可能的数据路径,并且在保持相同资源利用率的同时具有更快的重新配置。此外,通过对两种收缩阵列使用相同的遗传算法,结果表明HexCell阵列具有更高的吞吐量,并且可以比最先进的阵列更快地进化。
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HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on FPGAs: (Abstract Only)
This paper presents a novel cell architecture for evolvable systolic arrays. HexCell is a tile-able processing element with a hexagonal shape that can be implemented and dynamically reconfigured on field-programmable gate arrays (FPGAs). The cell contains a functional unit, three input ports, and three output ports. It supports two concurrent configuration schemes: dynamic partial reconfiguration (DPR), where the functional unit is partially reconfigured at run time, and virtual reconfiguration circuit (VRC), where the cell output port bypasses one of the input data or selects the functional unit output. Hence, HexCell combines the merits of DPR and VRC including resource-awareness, reconfiguration speed and routing flexibility. In addition, the cell structure supports pipelining and data synchronization for achieving high throughput for data-intensive applications like image processing. A HexCell is represented by a binary string (chromosome) that encodes the cell's function and the output selections. Our developed evolvable HexCell array supports more inputs and outputs, a variety of possible datapaths, and has faster reconfiguration, compared to the state-of-the-art systolic array while maintaining the same resource utilization. Moreover, by using the same genetic algorithm on the two systolic arrays, results show that the HexCell array has higher throughput and can evolve faster than state-of-the-art array.
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