基于FPGA的异步收发器实现

2012 Third Global Congress on Intelligent Systems Pub Date : 2012-11-06 DOI:10.1109/GCIS.2012.16

Xiao-li Hu, Feng-ying Wang, Bo Chen

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引用次数: 1

摘要

本文讨论了通用异步收发器的基本原理，并在EDA实验平台集成的altera NIOSII开发板上设计和实现了通用异步收发器。FPGA的主芯片型号为EP1C12F324C8。电路设计用VHDL硬件描述语言编程，开发软件是QuartusII9.0。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Implementation of Asynchronous Receiver/ Transmitter Based on FPGA

This article discusses the basic principles of the universal asynchronous receiver/transmitter, and design and realize of universal asynchronous receiver/transmitter base on Alter a NIOSII Development Board integrated in EDA experiment platform. the main chip Model of the FPGA is EP1C12F324C8. Circuit design with VHDL hardware description language programming, developing software is the QuartusII9.0.

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2012 Third Global Congress on Intelligent Systems

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