A low-noise fast-settling PLL frequency synthesizer for CDMA receivers

A 1.8-2 GHz fully integrated CMOS phase-locked-loop (PLL) frequency synthesizer for CDMA receivers is presented. The design focuses on the voltage controlled oscillator (VCO) and loop bandwidth adaptation technique, which determine the out-of-band phase noise and the speed of the PLL frequency synthesizer, respectively. A low power low phase noise bond wire VCO is proposed. The inductance compensation control circuit combined with the switched-capacitor array is used to automatically compensate the bond wire inductance variation. A novel lock detector that adoptively controls the loop bandwidth is employed. Implemented in a 0.18 /spl mu/m CMOS technology and at a 1.8 V supply voltage, the PLL frequency synthesizer dissipates 24 mW and occupies a chip area of 2.6 mm/spl times/1.6 mm. The simulation results show that phase noise of the synthesizer is -122.6 dBc/Hz at 1 MHz offset frequency and the settling time is 70 /spl mu/s.