{"title":"高性能低电压低功率电压模模拟倍增电路","authors":"T. Ettaghzouti, N. Hassen, K. Besbes","doi":"10.1109/DT.2017.8012160","DOIUrl":null,"url":null,"abstract":"This paper presents a low voltage low power analogue voltage mode four quadrant multiplier circuit using only two second generation current conveyor circuits (CCII) and two NMOS transistors operating in ohmic region. This circuit is characterized by ± 0.25 V dynamic ranges with a low total harmonic distortion (THD) around to 0.021 %, wide bandwidth (2.67 GHz) and low power consumption of about 0.43 mW. Tspice simulations using 0.18 µm CMOS TSMC parameters are performed to confirm the workability of CCII circuit and voltage mode multiplier structure.","PeriodicalId":426951,"journal":{"name":"2016 7th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications (SETIT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"High performance low voltage low power voltage mode analog multiplier circuit\",\"authors\":\"T. Ettaghzouti, N. Hassen, K. Besbes\",\"doi\":\"10.1109/DT.2017.8012160\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low voltage low power analogue voltage mode four quadrant multiplier circuit using only two second generation current conveyor circuits (CCII) and two NMOS transistors operating in ohmic region. This circuit is characterized by ± 0.25 V dynamic ranges with a low total harmonic distortion (THD) around to 0.021 %, wide bandwidth (2.67 GHz) and low power consumption of about 0.43 mW. Tspice simulations using 0.18 µm CMOS TSMC parameters are performed to confirm the workability of CCII circuit and voltage mode multiplier structure.\",\"PeriodicalId\":426951,\"journal\":{\"name\":\"2016 7th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications (SETIT)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 7th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications (SETIT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DT.2017.8012160\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 7th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications (SETIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DT.2017.8012160","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High performance low voltage low power voltage mode analog multiplier circuit
This paper presents a low voltage low power analogue voltage mode four quadrant multiplier circuit using only two second generation current conveyor circuits (CCII) and two NMOS transistors operating in ohmic region. This circuit is characterized by ± 0.25 V dynamic ranges with a low total harmonic distortion (THD) around to 0.021 %, wide bandwidth (2.67 GHz) and low power consumption of about 0.43 mW. Tspice simulations using 0.18 µm CMOS TSMC parameters are performed to confirm the workability of CCII circuit and voltage mode multiplier structure.
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