{"title":"用于神经信号采集的四通道模拟前端设计","authors":"Hu Shaonan, Qu Ruoyuan, Yang Haidong","doi":"10.1109/WARTIA.2014.6976525","DOIUrl":null,"url":null,"abstract":"A 4-channel analog front-ends designed for neural signal acquisition is demonstrated in this paper. Each channel consists of a high input impedance, high gain, low noise and high linearity amplifier and a high precision Σ-Δ analog to digital convertor (ADC). The amplifier is realized with a capacitive feedback closed loop op-amp. Fabricated in 180nm CMOS process, the 4-channel system occupies 2.34mm2 while achieving a resolution of 0.9μV and the equivalent input-referred noise of 3.06μV according to the chip test results.","PeriodicalId":288854,"journal":{"name":"2014 IEEE Workshop on Advanced Research and Technology in Industry Applications (WARTIA)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of 4-channel analog front-ends for neural signal acquisition\",\"authors\":\"Hu Shaonan, Qu Ruoyuan, Yang Haidong\",\"doi\":\"10.1109/WARTIA.2014.6976525\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 4-channel analog front-ends designed for neural signal acquisition is demonstrated in this paper. Each channel consists of a high input impedance, high gain, low noise and high linearity amplifier and a high precision Σ-Δ analog to digital convertor (ADC). The amplifier is realized with a capacitive feedback closed loop op-amp. Fabricated in 180nm CMOS process, the 4-channel system occupies 2.34mm2 while achieving a resolution of 0.9μV and the equivalent input-referred noise of 3.06μV according to the chip test results.\",\"PeriodicalId\":288854,\"journal\":{\"name\":\"2014 IEEE Workshop on Advanced Research and Technology in Industry Applications (WARTIA)\",\"volume\":\"162 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE Workshop on Advanced Research and Technology in Industry Applications (WARTIA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WARTIA.2014.6976525\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Workshop on Advanced Research and Technology in Industry Applications (WARTIA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WARTIA.2014.6976525","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of 4-channel analog front-ends for neural signal acquisition
A 4-channel analog front-ends designed for neural signal acquisition is demonstrated in this paper. Each channel consists of a high input impedance, high gain, low noise and high linearity amplifier and a high precision Σ-Δ analog to digital convertor (ADC). The amplifier is realized with a capacitive feedback closed loop op-amp. Fabricated in 180nm CMOS process, the 4-channel system occupies 2.34mm2 while achieving a resolution of 0.9μV and the equivalent input-referred noise of 3.06μV according to the chip test results.
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