时钟变化对数字控制系统性能的影响

S. Kuruppu, Alexander Shibilski
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引用次数: 1

摘要

由于半导体工业的进步和成本的降低,数字控制已成为许多应用中的主要控制形式。在数字信号处理器(dsp)或微控制器上实现的数字控制算法以指定的时钟频率执行算法。离散时间算法如数字滤波器和数字PID控制器在控制器设计中要求采样周期,这直接关系到单片机的时钟频率。由于老化,制造工艺缺陷和环境条件导致时钟频率偏离规范。这种变化会影响离散时间算法的性能偏离预期性能。
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Clock Variation Impact on Digital Control System Performance
Digital controls have become the primary form of control in numerous applications due to the advancements in semiconductor industry and lower cost. Digital control algorithms implemented on digital signal processors (DSPs) or microcontrollers execute the algorithm at a specified clock frequency. Discrete time algorithms such as digital filters and digital PID controllers require the sampling period in the controller design, which is directly related to the microcontroller clock frequency. Due to aging, manufacturing process defects and environment conditions cause the clock frequency to drift from the specification. Such variation affects the discrete time algorithm performance deviate from expected performance.
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