{"title":"采用0.8-/spl μ m光刻技术,形成极窄发射极(0.3 /spl μ m)双多晶硅双极晶体管的双间隔技术","authors":"C. Tsai, B. Scharf, P. Garone, P. Humphries, K. O","doi":"10.1109/BIPOL.1995.493875","DOIUrl":null,"url":null,"abstract":"Emitter widths of 0.3 /spl mu/m on double-polysilicon bipolar transistors are achieved using 0.8-/spl mu/m photolithography and a double-spacer process. The emitter width reduction is confirmed with structural and electrical measurements. The double-spacer device exhibits superior low current f/sub T/ and f/sub max/.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"87 5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A double-spacer technology for the formation of very narrow emitter (0.3 /spl mu/m) double-polysilicon bipolar transistors using 0.8-/spl mu/m photolithography\",\"authors\":\"C. Tsai, B. Scharf, P. Garone, P. Humphries, K. O\",\"doi\":\"10.1109/BIPOL.1995.493875\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Emitter widths of 0.3 /spl mu/m on double-polysilicon bipolar transistors are achieved using 0.8-/spl mu/m photolithography and a double-spacer process. The emitter width reduction is confirmed with structural and electrical measurements. The double-spacer device exhibits superior low current f/sub T/ and f/sub max/.\",\"PeriodicalId\":230944,\"journal\":{\"name\":\"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting\",\"volume\":\"87 5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1995.493875\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1995.493875","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A double-spacer technology for the formation of very narrow emitter (0.3 /spl mu/m) double-polysilicon bipolar transistors using 0.8-/spl mu/m photolithography
Emitter widths of 0.3 /spl mu/m on double-polysilicon bipolar transistors are achieved using 0.8-/spl mu/m photolithography and a double-spacer process. The emitter width reduction is confirmed with structural and electrical measurements. The double-spacer device exhibits superior low current f/sub T/ and f/sub max/.