{"title":"用于亚微米MOSFET制造的新边缘定义垂直蚀刻方法","authors":"W. Hunter, T. Holloway, P. Chatterjee, A. Tasch","doi":"10.1109/IEDM.1980.189949","DOIUrl":null,"url":null,"abstract":"This paper describes a new, convenient \"undercut and backfill\" technique for forming edge-defined submicrometer elements based only on standard optical lithography and vertical (anisotropic) dry etching. MOSFETs having physical channel lengths from0.3 \\microm to\\simeq 1.0 microm can be fabricated using this approach, This method is compared with an alternative vertical etch, edge-defined technique which is capable of fabricating physical gate lengths oF0.1-0.4 \\microm. In particular, MOSFETs havingL \\simeq 0.1 \\microm, believed to be the smallest reported to date, have been made. A vertical etching technique which forms a passivating sidewall oxide is also described. Modifications of this technique to fabricate self-aligned shallow/deep n+/n++ junctions having reduced series resistance and short-channel effects (in particular punchthrough) are illustrated.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"New edge-defined vertical-etch approaches for submicrometer MOSFET fabrication\",\"authors\":\"W. Hunter, T. Holloway, P. Chatterjee, A. Tasch\",\"doi\":\"10.1109/IEDM.1980.189949\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a new, convenient \\\"undercut and backfill\\\" technique for forming edge-defined submicrometer elements based only on standard optical lithography and vertical (anisotropic) dry etching. MOSFETs having physical channel lengths from0.3 \\\\microm to\\\\simeq 1.0 microm can be fabricated using this approach, This method is compared with an alternative vertical etch, edge-defined technique which is capable of fabricating physical gate lengths oF0.1-0.4 \\\\microm. In particular, MOSFETs havingL \\\\simeq 0.1 \\\\microm, believed to be the smallest reported to date, have been made. A vertical etching technique which forms a passivating sidewall oxide is also described. Modifications of this technique to fabricate self-aligned shallow/deep n+/n++ junctions having reduced series resistance and short-channel effects (in particular punchthrough) are illustrated.\",\"PeriodicalId\":180541,\"journal\":{\"name\":\"1980 International Electron Devices Meeting\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1980 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1980.189949\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1980.189949","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
New edge-defined vertical-etch approaches for submicrometer MOSFET fabrication
This paper describes a new, convenient "undercut and backfill" technique for forming edge-defined submicrometer elements based only on standard optical lithography and vertical (anisotropic) dry etching. MOSFETs having physical channel lengths from0.3 \microm to\simeq 1.0 microm can be fabricated using this approach, This method is compared with an alternative vertical etch, edge-defined technique which is capable of fabricating physical gate lengths oF0.1-0.4 \microm. In particular, MOSFETs havingL \simeq 0.1 \microm, believed to be the smallest reported to date, have been made. A vertical etching technique which forms a passivating sidewall oxide is also described. Modifications of this technique to fabricate self-aligned shallow/deep n+/n++ junctions having reduced series resistance and short-channel effects (in particular punchthrough) are illustrated.