{"title":"在可重构CPU+FPGA平台上实现DSP多通道相关的可行性研究","authors":"M. Leonov, V. V. Kitaev","doi":"10.1109/PDCAT.2008.62","DOIUrl":null,"url":null,"abstract":"The paper provides an insight to implementation framework and a test-bed of multi-channel correlation on high-performance CPU+FPGA hybrid platform. Solution based on commodity PC, PCIe Altera Stratix II GX board, and C-to-HDL tool has been demonstrated.","PeriodicalId":282779,"journal":{"name":"2008 Ninth International Conference on Parallel and Distributed Computing, Applications and Technologies","volume":"83 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Feasibility Study of Implementing Multi-Channel Correlation for DSP Applications on Reconfigurable CPU+FPGA Platform\",\"authors\":\"M. Leonov, V. V. Kitaev\",\"doi\":\"10.1109/PDCAT.2008.62\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper provides an insight to implementation framework and a test-bed of multi-channel correlation on high-performance CPU+FPGA hybrid platform. Solution based on commodity PC, PCIe Altera Stratix II GX board, and C-to-HDL tool has been demonstrated.\",\"PeriodicalId\":282779,\"journal\":{\"name\":\"2008 Ninth International Conference on Parallel and Distributed Computing, Applications and Technologies\",\"volume\":\"83 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 Ninth International Conference on Parallel and Distributed Computing, Applications and Technologies\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PDCAT.2008.62\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 Ninth International Conference on Parallel and Distributed Computing, Applications and Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PDCAT.2008.62","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
给出了多通道相关在高性能CPU+FPGA混合平台上的实现框架和测试平台。演示了基于商用PC机、PCIe Altera Stratix II GX板和C-to-HDL工具的解决方案。
Feasibility Study of Implementing Multi-Channel Correlation for DSP Applications on Reconfigurable CPU+FPGA Platform
The paper provides an insight to implementation framework and a test-bed of multi-channel correlation on high-performance CPU+FPGA hybrid platform. Solution based on commodity PC, PCIe Altera Stratix II GX board, and C-to-HDL tool has been demonstrated.