Discriminatively Fortified Computing with Reconfigurable Digital Fabric

This work proposes a novel approach -- Discriminatively Fortified Computing (DFC) -- to achievehardware-efficient reliable computing without deterministically knowing the location and occurrence time of hardware defects and design faults. The key insights behind DFC comprise:1) different system components contribute differently to the overall correctness of a target application, therefore should be treated distinctively, and 2) abundant error resilience exists inherently in many practical algorithms, such as signal processing, visual perception, and artificial learning. Such error resilience can be significantly improved with effective hardware support. The major contributions of this work include 1) the development of a complete methodology to perform sensitivity and criticality analysis of hardware redundancy, 2) a novel problem formulation and an efficient heuristic methodology to discriminatively allocate hardware redundancy among a targetdesign's key components in order to maximize its overall error resilience, 3) an academic prototype of DFC computing device that illustrates a 4 times improvement of error resilience for aH.264 encoder implemented with an FPGA device.