M. Urano, T. Douseki, T. Hatano, H. Fukuda, M. Harada, T. Tsuchiya
{"title":"一种超低电压MTCMOS/SIMOX栅极阵列","authors":"M. Urano, T. Douseki, T. Hatano, H. Fukuda, M. Harada, T. Tsuchiya","doi":"10.1109/ASIC.1997.616968","DOIUrl":null,"url":null,"abstract":"An ultra-low-voltage gate array has been developed using a multi-threshold CMOS (MTCMOS) circuit and separation by implanted oxygen (SIMOX) technology, which is a type of a silicon-on-insulator (SOI) technology. A 250-K basic-cell gate array was fabricated using 0.25-/spl mu/m MTCMOS/SIMOX technology. The gate delay time is 140 ps at 1.2 V and 470 ps at 0.5 V. A 30-KG test circuit was fabricated and the same operating speed as that of 0.5-/spl mu/m at 3.3 V (i.e., 25 MHz) was obtained at 0.58 V with the power consumption reduced to 1/100. At 0.76 V, the operating speed was 40 MHz.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An ultra-low-voltage MTCMOS/SIMOX gate array\",\"authors\":\"M. Urano, T. Douseki, T. Hatano, H. Fukuda, M. Harada, T. Tsuchiya\",\"doi\":\"10.1109/ASIC.1997.616968\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An ultra-low-voltage gate array has been developed using a multi-threshold CMOS (MTCMOS) circuit and separation by implanted oxygen (SIMOX) technology, which is a type of a silicon-on-insulator (SOI) technology. A 250-K basic-cell gate array was fabricated using 0.25-/spl mu/m MTCMOS/SIMOX technology. The gate delay time is 140 ps at 1.2 V and 470 ps at 0.5 V. A 30-KG test circuit was fabricated and the same operating speed as that of 0.5-/spl mu/m at 3.3 V (i.e., 25 MHz) was obtained at 0.58 V with the power consumption reduced to 1/100. At 0.76 V, the operating speed was 40 MHz.\",\"PeriodicalId\":300310,\"journal\":{\"name\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1997.616968\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.616968","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An ultra-low-voltage gate array has been developed using a multi-threshold CMOS (MTCMOS) circuit and separation by implanted oxygen (SIMOX) technology, which is a type of a silicon-on-insulator (SOI) technology. A 250-K basic-cell gate array was fabricated using 0.25-/spl mu/m MTCMOS/SIMOX technology. The gate delay time is 140 ps at 1.2 V and 470 ps at 0.5 V. A 30-KG test circuit was fabricated and the same operating speed as that of 0.5-/spl mu/m at 3.3 V (i.e., 25 MHz) was obtained at 0.58 V with the power consumption reduced to 1/100. At 0.76 V, the operating speed was 40 MHz.
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