通过字级压缩实现PCM的细粒度受限Coset编码

Seyed Mohammad Seyedzadeh, A. Jones, R. Melhem
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引用次数: 14

摘要

相变存储器(PCM)最近作为一种有前途的技术出现,以满足计算机系统对大容量存储器快速增长的需求,取代了受物理限制阻碍的DRAM。多层单元(MLC) PCM提供高密度和低每字节制造成本。然而,尽管有许多优点,如可扩展性和低泄漏,编程中间状态的能量比编程单电平单元PCM要大得多。在本文中,我们研究了当编码粒度低于典型的缓存线大小时,如何减少MLC PCM的写入能量。我们观察到,以小粒度编码数据块以减少写入能量实际上增加了写入能量,因为辅助编码位。我们通过以下方法减轻了这种不利影响:1)设计合适的码字映射,使用更少的辅助位;2)提出一种新的字级压缩(WLC),它压缩了91%以上的存储行,并提供了足够的空间来存储辅助数据,使用了一种新的限制性协集编码,应用于小数据块粒度。实验结果表明,在16位数据粒度下,与现有的编码方法相比,所提出的编码方法平均减少了39%的写能量。此外,它的续航能力提高了20%,比现有的方法更可靠。硬件综合评估表明,所提出的编码可以在片上实现,只有一个名义上的面积开销。
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Enabling Fine-Grain Restricted Coset Coding Through Word-Level Compression for PCM
Phase change memory (PCM) has recently emerged as a promising technology to meet the fast growing demand for large capacity memory in computer systems, replacing DRAM that is impeded by physical limitations. Multi-level cell (MLC) PCM offers high density with low per-byte fabrication cost. However, despite many advantages, such as scalability and low leakage, the energy for programming intermediate states is considerably larger than programing single-level cell PCM. In this paper, we study encoding techniques to reduce write energy for MLC PCM when the encoding granularity is lowered below the typical cache line size. We observe that encoding data blocks at small granularity to reduce write energy actually increases the write energy because of the auxiliary encoding bits. We mitigate this adverse effect by 1) designing suitable codeword mappings that use fewer auxiliary bits and 2) proposing a new Word-Level Compression (WLC) which compresses more than 91% of the memory lines and provides enough room to store the auxiliary data using a novel restricted coset encoding applied at small data block granularities. Experimental results show that the proposed encoding at 16-bit data granularity reduces the write energy by 39%, on average, versus the leading encoding approach for write energy reduction. Furthermore, it improves endurance by 20% and is more reliable than the leading approach. Hardware synthesis evaluation shows that the proposed encoding can be implemented on-chip with only a nominal area overhead.
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