{"title":"一种用于多天线直接转换收发器系统的带倍频的数字控制CMOS移相器","authors":"Karthik Tripurari, M. Banu, P. Kinget","doi":"10.1109/RWS.2011.5725463","DOIUrl":null,"url":null,"abstract":"A digitally controlled frequency-doubling phase-shifter architecture is presented for the implementation of multiple-antenna GHz transceiver systems. It takes a 1.75GHz input and produces two phase-shifted outputs at 3.5GHz. It consists of a Delay Locked Loop (DLL) followed by symmetric XOR frequency doublers and phase interpolators. The phase shifter prototype in 90nm standard CMOS has a phase shift range of 360° with a resolution of 22.5° and an INL < 12° (< 4° with external adjust), and consumes 55mW from a 1V supply.","PeriodicalId":250672,"journal":{"name":"2011 IEEE Radio and Wireless Symposium","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A digitally controlled CMOS phase shifter with frequency doubling for multiple-antenna, direct-conversion transceiver systems\",\"authors\":\"Karthik Tripurari, M. Banu, P. Kinget\",\"doi\":\"10.1109/RWS.2011.5725463\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A digitally controlled frequency-doubling phase-shifter architecture is presented for the implementation of multiple-antenna GHz transceiver systems. It takes a 1.75GHz input and produces two phase-shifted outputs at 3.5GHz. It consists of a Delay Locked Loop (DLL) followed by symmetric XOR frequency doublers and phase interpolators. The phase shifter prototype in 90nm standard CMOS has a phase shift range of 360° with a resolution of 22.5° and an INL < 12° (< 4° with external adjust), and consumes 55mW from a 1V supply.\",\"PeriodicalId\":250672,\"journal\":{\"name\":\"2011 IEEE Radio and Wireless Symposium\",\"volume\":\"70 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-03-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE Radio and Wireless Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RWS.2011.5725463\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE Radio and Wireless Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RWS.2011.5725463","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A digitally controlled CMOS phase shifter with frequency doubling for multiple-antenna, direct-conversion transceiver systems
A digitally controlled frequency-doubling phase-shifter architecture is presented for the implementation of multiple-antenna GHz transceiver systems. It takes a 1.75GHz input and produces two phase-shifted outputs at 3.5GHz. It consists of a Delay Locked Loop (DLL) followed by symmetric XOR frequency doublers and phase interpolators. The phase shifter prototype in 90nm standard CMOS has a phase shift range of 360° with a resolution of 22.5° and an INL < 12° (< 4° with external adjust), and consumes 55mW from a 1V supply.
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