用于射频应用的低压CMOS乘法器

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) Pub Date : 2000-07-26 DOI:10.1145/344166.344598

Carl J. Debono, Franco Maloberti, J. Micallef

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引用次数: 6

摘要

提出了一种工作电压为1.2 V的低压模拟乘法器。乘法器核心由四个在饱和区工作的MOS晶体管组成。该电路利用了MOS晶体管在饱和状态下电流与电压的二次关系。电路采用标准的0.6 /spl mu/m CMOS工艺设计。仿真结果表明，IP3为4.9 dBm，无杂散动态范围为45 dB。

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A low-voltage CMOS multiplier for RF applications

A low-voltage analog multiplier operating at 1.2 V is presented. The multiplier core consists of four MOS transistors operating in the saturation region. The circuit exploits the quadratic relation between current and voltage of the MOS transistor in saturation. The circuit was designed using standard 0.6 /spl mu/m CMOS technology. Simulation results indicate an IP3 of 4.9 dBm and a spur free dynamic range of 45 dB.

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ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)

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