Reliability aware self-healing FFT system employing partial reconfiguration for reduced power consumption

The very high levels of integration and submicron device sizes used in emerging VLSI systems and FPGAs lead to frequent occurrences of defects and operational faults. Thus, the need for fault tolerance and reliability of deployed systems becomes increasingly prominent. This paper discusses fault tolerance and reliability observed in the design of a parallel self-healing VLSI system, based on partial dynamic reconfiguration (PDR) and built-in-self-test (BIST) for delay/stuck-at faults. PDR is employed to keep the system on line while under repair, for reduced power consumption and also to reduce repair time. Results prove that, a self-healing FFT prototype system implemented on Virtex6 FPGA can tolerate stressful sequences of injected delay and permanent faults with nominal impact on the system performance (hardware overhead and delay). The review of research proves that the proposed system is ideal for VLSI implementations of low power application fault tolerant systems.