始终并行:高性能ssd的平面级并行探索

Congming Gao, Liang Shi, C. Xue, Cheng Ji, Jun Yang, Youtao Zhang
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引用次数: 13

摘要

固态硬盘(ssd)是由多层并行组织构成的,包括通道、芯片、模具和平面。在这些并行级别中,平面级并行是ssd的最后一级并行,限制最严格。只有访问不同平面的同一地址的同一类型的操作才能并行处理。为了最大限度地提高访问性能,人们已经提出了一些利用平面级并行性进行主机访问和ssd内部操作的研究。然而,我们的初步研究表明,平面水平的并行性远远没有得到很好的利用,需要进一步改进。其原因是平面平行度的严格限制难以满足。本文提出了一种从平面到模具的并行优化框架,通过始终巧妙地满足严格的约束条件来开发平面级并行性。为了实现这一目标,至少有两个挑战。首先,由于主机访问模式总是复杂的,因此同时接收多个相同类型的请求到不同的平面是不常见的。其次,存在许多内部活动,例如垃圾收集(GC),这可能会破坏这些限制。为了解决上述挑战,在SSD控制器中提出了两种方案:首先,设计了一个芯片级的写构造方案,以确保每次写操作始终有N页的数据写入。其次,在进一步的步骤中,提出了一种模具级GC方案,以同一模具中所有平面为单位激活GC。结合die级写和die级GC,来自主机写操作和GC诱导的有效页面移动的写访问可以在任何时候并行处理。因此,可以显著降低GC成本和平均写延迟。实验结果表明,该框架能够在不影响读性能的情况下显著提高写性能。
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Parallel all the time: Plane Level Parallelism Exploration for High Performance SSDs
Solid state drives (SSDs) are constructed with multiple level parallel organization, including channels, chips, dies and planes. Among these parallel levels, plane level parallelism, which is the last level parallelism of SSDs, has the most strict restrictions. Only the same type of operations which access the same address in different planes can be processed in parallel. In order to maximize the access performance, several previous works have been proposed to exploit the plane level parallelism for host accesses and internal operations of SSDs. However, our preliminary studies show that the plane level parallelism is far from well utilized and should be further improved. The reason is that the strict restrictions of plane level parallelism are hard to be satisfied. In this work, a from plane to die parallel optimization framework is proposed to exploit the plane level parallelism through smartly satisfying the strict restrictions all the time. In order to achieve the objective, there are at least two challenges. First, due to that host access patterns are always complex, receiving multiple same-type requests to different planes at the same time is uncommon. Second, there are many internal activities, such as garbage collection (GC), which may destroy the restrictions. In order to solve above challenges, two schemes are proposed in the SSD controller: First, a die level write construction scheme is designed to make sure there are always N pages of data written by each write operation. Second, in a further step, a die level GC scheme is proposed to activate GC in the unit of all planes in the same die. Combing the die level write and die level GC, write accesses from both host write operations and GC induced valid page movements can be processed in parallel at all time. As a result, the GC cost and average write latency can be significantly reduced. Experiment results show that the proposed framework is able to significantly improve the write performance without read performance impact.
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