{"title":"一种用于ATM网络接口的RISC核心设计","authors":"A. Elkateeb, M. Elbeshti","doi":"10.1109/PACRIM.1999.799600","DOIUrl":null,"url":null,"abstract":"The embedded RISC core can be used efficiently to design high-speed scalable ATM network interfaces. Such core could also make the design of these interfaces simple, shorten the developing cycle and reduce their developing cost. In this paper, we have studied the design issues related to reduced instruction set computer (RISC) core and specifically for high-speed ATM host-network interfaces applications. We have investigated the processing and the instruction types that the RISC core is usually performed in addition to its structure.","PeriodicalId":176763,"journal":{"name":"1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368)","volume":"26 12","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A RISC core design for an ATM network interfaces\",\"authors\":\"A. Elkateeb, M. Elbeshti\",\"doi\":\"10.1109/PACRIM.1999.799600\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The embedded RISC core can be used efficiently to design high-speed scalable ATM network interfaces. Such core could also make the design of these interfaces simple, shorten the developing cycle and reduce their developing cost. In this paper, we have studied the design issues related to reduced instruction set computer (RISC) core and specifically for high-speed ATM host-network interfaces applications. We have investigated the processing and the instruction types that the RISC core is usually performed in addition to its structure.\",\"PeriodicalId\":176763,\"journal\":{\"name\":\"1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368)\",\"volume\":\"26 12\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-08-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PACRIM.1999.799600\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PACRIM.1999.799600","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The embedded RISC core can be used efficiently to design high-speed scalable ATM network interfaces. Such core could also make the design of these interfaces simple, shorten the developing cycle and reduce their developing cost. In this paper, we have studied the design issues related to reduced instruction set computer (RISC) core and specifically for high-speed ATM host-network interfaces applications. We have investigated the processing and the instruction types that the RISC core is usually performed in addition to its structure.
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