利用固态硬盘地址转换的内部并行性

Wei Xie, Yong Chen, P. Roth
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引用次数: 8

摘要

固态硬盘(ssd)已经改变了存储系统的格局,与传统硬盘驱动器相比,由于其低延迟、高带宽和低功耗,它为数据密集型应用程序提供了一个有前途的存储解决方案。ssd通过内部并行(对多个内部闪存芯片的并行访问)和一个闪存转换层(FTL)来实现这些理想的特性,该转换层确定数据存储在这些芯片上的位置,从而使它们不会过早磨损。然而,当前最先进的基于缓存的ftl,如基于需求的闪存转换层(DFTL),不允许IO调度器充分利用内部并行性,因为它们在逻辑到物理地址转换和数据访问之间施加了紧密耦合。为了解决这一限制,我们引入了一种新的FTL设计,称为Parallel-DFTL,它与DFTL一起将地址转换操作与数据访问解耦。Parallel-DFTL将地址转换和数据访问操作分离到不同的队列中,允许SSD对这两种操作使用并发的闪存访问。我们还提出了一种并行lru缓存替换算法,以提高地址转换操作的并发性。为了将Parallel-DFTL与现有的FTL方法进行比较,我们提出了一个Parallel-DFTL性能模型,并将其预测结果与DFTL和一种理想的页面映射方法进行比较。我们还使用真实设备参数在SSD模拟器中实现了Parallel-DFTL方法,并使用跟踪驱动仿真来评估Parallel-DFTL的有效性。我们的评估结果表明,对于我们测试的真实IO工作负载,Parallel-DFTL将总体性能提高了32%,对于合成测试工作负载,则提高了两个数量级。我们还发现Parallel-DFTL能够在非常小的缓存大小下实现合理的性能,并且它为那些请求大小大或写比率高的工作负载提供了最佳的好处。
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Exploiting Internal Parallelism for Address Translation in Solid-State Drives
Solid-state Drives (SSDs) have changed the landscape of storage systems and present a promising storage solution for data-intensive applications due to their low latency, high bandwidth, and low power consumption compared to traditional hard disk drives. SSDs achieve these desirable characteristics using internal parallelism—parallel access to multiple internal flash memory chips—and a Flash Translation Layer (FTL) that determines where data are stored on those chips so that they do not wear out prematurely. However, current state-of-the-art cache-based FTLs like the Demand-based Flash Translation Layer (DFTL) do not allow IO schedulers to take full advantage of internal parallelism, because they impose a tight coupling between the logical-to-physical address translation and the data access. To address this limitation, we introduce a new FTL design called Parallel-DFTL that works with the DFTL to decouple address translation operations from data accesses. Parallel-DFTL separates address translation and data access operations into different queues, allowing the SSD to use concurrent flash accesses for both types of operations. We also present a Parallel-LRU cache replacement algorithm to improve the concurrency of address translation operations. To compare Parallel-DFTL against existing FTL approaches, we present a Parallel-DFTL performance model and compare its predictions against those for DFTL and an ideal page-mapping approach. We also implemented the Parallel-DFTL approach in an SSD simulator using real device parameters, and used trace-driven simulation to evaluate Parallel-DFTL’s efficacy. Our evaluation results show that Parallel-DFTL improved the overall performance by up to 32% for the real IO workloads we tested, and by up to two orders of magnitude with synthetic test workloads. We also found that Parallel-DFTL is able to achieve reasonable performance with a very small cache size and that it provides the best benefit for those workloads with large request size or with high write ratio.
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