三维模堆技术中的高性能无阻塞开关设计

D. L. Lewis, S. Yalamanchili, H. Lee
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引用次数: 18

摘要

芯片堆叠技术是一种很有前途的新技术,可以实现器件在三维空间的集成。它允许多个活动层直接堆叠在另一个层的顶部,通过短而密集的模对模通道提供通信。以前的工作已经在所有设计目标上显示了显著的好处,从在逻辑上堆叠内存到跨多层划分单个架构单元。许多高速处理器单元——alu、寄存器、缓存和指令调度器——都采用了3D设计,实现了显著的节能和性能提升。其他工作着眼于在芯片堆栈中实现片上网络,但将重点限制在各种单元(处理器,路由器等)的平面设计上。本工作在这两个研究领域的基础上,探索路由器部件的三维设计,特别是横杆的三维设计。我们研究了交叉杆和两个多级互连网络的实现,以确定3D实现的潜在好处。与同等平面设计相比,我们实现了最大延迟减少26%和最大功耗节省24%。
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High Performance Non-blocking Switch Design in 3D Die-Stacking Technology
Die stacking is a promising new technology that enables integration of devices in the third dimension. It allows the stacking of multiple active layers directly on top of one another with short, dense die-to-die vias providing communication. Previous work has shown significant bene¿ts at all design targets, from stacking memory on logic to partitioning individual architectural units across multiple layers. Many high-speed processor units—ALUs, register ¿les, caches, and instruction schedulers—have all been designed in 3D, achieving signi¿cant, simultaneous power savings and performance boosts. Other work has looked at the implementation of network-on-chip in a die stack but restricted the focus to planar designs of the various unit(processors, routers, etc.). This work follows up on these two re-search areas to explore the 3D design of router components, speci¿cally the crossbar. We examine the implementation of a crossbar and two multistage interconnect networks to determine the potential bene¿ts of 3D implementations. Compared to equivalent planar designs,we achieve a maximum delay reduction of 26% and maximum power savings of 24%.
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