FPGA的SSN和抖动测量与分析

H. Fujita, Y. Iijima, T. Sudo
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引用次数: 2

摘要

寄生电感存在于一个封装引起SSN(同步开关噪声)和时序抖动。这些噪声会导致LSI和系统的故障。本文的目的是通过改变同时开关缓冲器的数量和相邻缓冲器反向交替的数量来阐明包括互感在内的封装有效电感的影响。在本研究中,通过HSPICE模拟再现了测量到的ssn。整个仿真模型包括片上PDN (Power Distribution Network)、封装PDN和板上PDN,以及I/O缓冲模型。模拟的SSN波形与实测结果吻合较好。
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Measurement and analysis of SSN and Jitter of FPGA
Parasitic inductance that exists in a package induces SSN (Simultaneous Switching Noise) and timing jitter. These noises cause malfunction of LSI and systems. The goal of this paper is to clarify the influence of the effective inductance of the package including mutual inductance by changing the number of simultaneously switching buffers and alternating adjacent buffers in the reverse direction each other. In this study, measured SSNs were reproduced by HSPICE simulation. The whole simulation model consisted of on-chip PDN (Power Distribution Network), package PDN and board PDN, along with I/O buffer model. The simulated SSN waveforms agreed well with the measured results.
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