Y.B. Cho, K.C. Lee, Yoshiyasu Takefuji, N. Funabiki
{"title":"利用开关电容技术模拟最大神经网络电路","authors":"Y.B. Cho, K.C. Lee, Yoshiyasu Takefuji, N. Funabiki","doi":"10.1109/IJCNN.1991.170652","DOIUrl":null,"url":null,"abstract":"The circuit of the maximum neural network based on the switched capacitor technique is proposed. The performance of the proposed circuit was derived from SPICE simulation. The bipartite subgraph problem is solved by using the proposed circuit. The SPICE simulation result confirms the function of the network. Because the complexity of the proposed analog circuit is so small, it is possible to fabricate an optimization system in a single chip.<<ETX>>","PeriodicalId":211135,"journal":{"name":"[Proceedings] 1991 IEEE International Joint Conference on Neural Networks","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Analog maximum neural network circuits using the switched capacitor technique\",\"authors\":\"Y.B. Cho, K.C. Lee, Yoshiyasu Takefuji, N. Funabiki\",\"doi\":\"10.1109/IJCNN.1991.170652\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The circuit of the maximum neural network based on the switched capacitor technique is proposed. The performance of the proposed circuit was derived from SPICE simulation. The bipartite subgraph problem is solved by using the proposed circuit. The SPICE simulation result confirms the function of the network. Because the complexity of the proposed analog circuit is so small, it is possible to fabricate an optimization system in a single chip.<<ETX>>\",\"PeriodicalId\":211135,\"journal\":{\"name\":\"[Proceedings] 1991 IEEE International Joint Conference on Neural Networks\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[Proceedings] 1991 IEEE International Joint Conference on Neural Networks\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IJCNN.1991.170652\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] 1991 IEEE International Joint Conference on Neural Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IJCNN.1991.170652","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analog maximum neural network circuits using the switched capacitor technique
The circuit of the maximum neural network based on the switched capacitor technique is proposed. The performance of the proposed circuit was derived from SPICE simulation. The bipartite subgraph problem is solved by using the proposed circuit. The SPICE simulation result confirms the function of the network. Because the complexity of the proposed analog circuit is so small, it is possible to fabricate an optimization system in a single chip.<>