{"title":"基于可编程逻辑器件的脉冲位置调制系统设计","authors":"Yuting Liu","doi":"10.1117/12.2640750","DOIUrl":null,"url":null,"abstract":"A communication system for remote communication is designed. The system uses FPGA as the main control unit and pulse position modulation PPM as the basic modulation mode. Aiming at the problem that frame synchronization can not be realized in PPM communication, this design adopts the way of adding frame head frame tail structure and inserting protection gap to ensure information synchronization. In addition, the four-phase clock synchronization extraction method is used in the synchronous demodulation of PPM signal at the receiving end, which effectively reduces the error rate of FPGA in the working process, and greatly simplifies the design of the whole system. In this design, the encoding of PPM will use Gray code mapping to reduce the bit error rate. Finally, the system achieves a faster communication rate, and the BER of the actual test is low.","PeriodicalId":336892,"journal":{"name":"Neural Networks, Information and Communication Engineering","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of pulse position modulation system based on programmable logic device\",\"authors\":\"Yuting Liu\",\"doi\":\"10.1117/12.2640750\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A communication system for remote communication is designed. The system uses FPGA as the main control unit and pulse position modulation PPM as the basic modulation mode. Aiming at the problem that frame synchronization can not be realized in PPM communication, this design adopts the way of adding frame head frame tail structure and inserting protection gap to ensure information synchronization. In addition, the four-phase clock synchronization extraction method is used in the synchronous demodulation of PPM signal at the receiving end, which effectively reduces the error rate of FPGA in the working process, and greatly simplifies the design of the whole system. In this design, the encoding of PPM will use Gray code mapping to reduce the bit error rate. Finally, the system achieves a faster communication rate, and the BER of the actual test is low.\",\"PeriodicalId\":336892,\"journal\":{\"name\":\"Neural Networks, Information and Communication Engineering\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Neural Networks, Information and Communication Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1117/12.2640750\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Neural Networks, Information and Communication Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1117/12.2640750","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of pulse position modulation system based on programmable logic device
A communication system for remote communication is designed. The system uses FPGA as the main control unit and pulse position modulation PPM as the basic modulation mode. Aiming at the problem that frame synchronization can not be realized in PPM communication, this design adopts the way of adding frame head frame tail structure and inserting protection gap to ensure information synchronization. In addition, the four-phase clock synchronization extraction method is used in the synchronous demodulation of PPM signal at the receiving end, which effectively reduces the error rate of FPGA in the working process, and greatly simplifies the design of the whole system. In this design, the encoding of PPM will use Gray code mapping to reduce the bit error rate. Finally, the system achieves a faster communication rate, and the BER of the actual test is low.