Furqan Zahoor, T. Zulkifli, F. A. Khanday, Aabid Amin Fida
{"title":"以CNTFET为存取元件的低功耗RRAM 1T1R阵列设计","authors":"Furqan Zahoor, T. Zulkifli, F. A. Khanday, Aabid Amin Fida","doi":"10.1109/SCORED.2019.8896306","DOIUrl":null,"url":null,"abstract":"A SPICE model of metal oxide based resistive random access memory (RRAM) devices is demonstrated in this paper having bipolar switching characteristics and utilizing carbon nanotube field effect transistor (CNTFET) in a 1T1R configuration. The growth and the dissolution of the conductive filament in the oxide layer is the basis of the switching mechanism in this model. The model has been implemented in HSPICE simulation software for circuit level analysis. Initially, the simulation of memory cell with CNTFETs is carried out and later on 3*3 memory matrix is analyzed. The proposed design shows a reduction in power consumption as compared to RRAM cell utilizing metal oxide semiconductor field effect transistor (MOSFET) in a 1T1R configuration.","PeriodicalId":231004,"journal":{"name":"2019 IEEE Student Conference on Research and Development (SCOReD)","volume":"166 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Low-power RRAM Device based 1T1R Array Design with CNTFET as Access Device\",\"authors\":\"Furqan Zahoor, T. Zulkifli, F. A. Khanday, Aabid Amin Fida\",\"doi\":\"10.1109/SCORED.2019.8896306\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A SPICE model of metal oxide based resistive random access memory (RRAM) devices is demonstrated in this paper having bipolar switching characteristics and utilizing carbon nanotube field effect transistor (CNTFET) in a 1T1R configuration. The growth and the dissolution of the conductive filament in the oxide layer is the basis of the switching mechanism in this model. The model has been implemented in HSPICE simulation software for circuit level analysis. Initially, the simulation of memory cell with CNTFETs is carried out and later on 3*3 memory matrix is analyzed. The proposed design shows a reduction in power consumption as compared to RRAM cell utilizing metal oxide semiconductor field effect transistor (MOSFET) in a 1T1R configuration.\",\"PeriodicalId\":231004,\"journal\":{\"name\":\"2019 IEEE Student Conference on Research and Development (SCOReD)\",\"volume\":\"166 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE Student Conference on Research and Development (SCOReD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SCORED.2019.8896306\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Student Conference on Research and Development (SCOReD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SCORED.2019.8896306","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low-power RRAM Device based 1T1R Array Design with CNTFET as Access Device
A SPICE model of metal oxide based resistive random access memory (RRAM) devices is demonstrated in this paper having bipolar switching characteristics and utilizing carbon nanotube field effect transistor (CNTFET) in a 1T1R configuration. The growth and the dissolution of the conductive filament in the oxide layer is the basis of the switching mechanism in this model. The model has been implemented in HSPICE simulation software for circuit level analysis. Initially, the simulation of memory cell with CNTFETs is carried out and later on 3*3 memory matrix is analyzed. The proposed design shows a reduction in power consumption as compared to RRAM cell utilizing metal oxide semiconductor field effect transistor (MOSFET) in a 1T1R configuration.
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