{"title":"具有纠错码的指令级时间冗余容错体系结构","authors":"Chao Yan, Hongjun Dai, Tianzhou Chen, Meikang Qiu","doi":"10.1109/EUC.2010.124","DOIUrl":null,"url":null,"abstract":"Soft error has become an increasingly significant problem in modern computing systems. To overcome soft errors, it has reported that the instruction-level temporal redundancy in out-of-order cores suffers a performance penalty up to 45%. In this work, we propose the fault-tolerant double execution architecture with the fast error correcting code (such as two-dimensional error code) in the instruction reuse buffer. Experimental results show that it gains back IPC loss between 9.14% and 10.15%, with an average around 9.22% compared with the conventional double execution approach.","PeriodicalId":265175,"journal":{"name":"2010 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2010-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Fault-tolerant Architecture with Error Correcting Code for the Instruction-level Temporal Redundancy\",\"authors\":\"Chao Yan, Hongjun Dai, Tianzhou Chen, Meikang Qiu\",\"doi\":\"10.1109/EUC.2010.124\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Soft error has become an increasingly significant problem in modern computing systems. To overcome soft errors, it has reported that the instruction-level temporal redundancy in out-of-order cores suffers a performance penalty up to 45%. In this work, we propose the fault-tolerant double execution architecture with the fast error correcting code (such as two-dimensional error code) in the instruction reuse buffer. Experimental results show that it gains back IPC loss between 9.14% and 10.15%, with an average around 9.22% compared with the conventional double execution approach.\",\"PeriodicalId\":265175,\"journal\":{\"name\":\"2010 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EUC.2010.124\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUC.2010.124","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Fault-tolerant Architecture with Error Correcting Code for the Instruction-level Temporal Redundancy
Soft error has become an increasingly significant problem in modern computing systems. To overcome soft errors, it has reported that the instruction-level temporal redundancy in out-of-order cores suffers a performance penalty up to 45%. In this work, we propose the fault-tolerant double execution architecture with the fast error correcting code (such as two-dimensional error code) in the instruction reuse buffer. Experimental results show that it gains back IPC loss between 9.14% and 10.15%, with an average around 9.22% compared with the conventional double execution approach.