降低高速/spl Sigma//spl Delta/带通调制器的功耗

P. Cusinato, F. Stefani, A. Baschirotto
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引用次数: 0

摘要

功耗是高速开关电容(SC)电路设计中的一个关键问题,它可以有效地实现许多模拟功能。其中,SC /spl Sigma//spl Delta/调制器在A/D转换中非常流行:在这类电路中,运算放大器是消耗最多的单元,因为它们在直流增益和单位增益频率方面都有要求。提出了一种直流增益为110 dB、单位增益频率为250 MHz的新型放大器。大功耗(20兆瓦)使得其在商业应用中的使用至关重要:然而,将这种电池与快速自适应偏置电路相结合,可以在合理的耗散下实现高性能。该方法已用于设计6阶带通/spl Sigma//spl Delta/调制器,该调制器具有73 dB DR,适用于调频无线电信号的中频(10.7 MHz)转换。
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Power consumption reduction in high-speed /spl Sigma//spl Delta/ bandpass modulators
Power consumption is a key point in the design of high-speed switched capacitor (SC) circuits, which allow to efficiently implement a number of analog functions. Among them, SC /spl Sigma//spl Delta/ modulators are very popular for A/D conversion: in this kind of circuits, operational amplifiers are the most consuming cells because of their requirements in terms of DC gain and unity-gain frequency. A new amplifier with 110 dB DC gain and a unity-gain frequency of 250 MHz is presented. The large power consumption (20 mW) makes critical its use in commercial applications: however, combining this cell with a fast adaptive biasing circuit, high performance may be achieved with a reasonable dissipation. This approach has been used in the design of a 6th-order bandpass /spl Sigma//spl Delta/ modulator featuring 73 dB DR and suitable for the conversion at IF (10.7 MHz) of the FM radio signal.
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