{"title":"嵌入式多媒体应用程序的16位浮点指令","authors":"L. Lacassagne, D. Etiemble, S. A. O. Kablia","doi":"10.1109/CAMP.2005.1","DOIUrl":null,"url":null,"abstract":"We have simulated the implementation of 16-bit floating point instructions on a Pentium4 and PowerPC G4 and G5 to evaluate the performance impact of these instructions in embedded processors for graphics and multimedia applications. Both accuracy of the computations and the execution time have been considered. For low-end embedded processors, the 16-bit FP instructions deliver a larger dynamic range than 16-bit integer with the same memory footprint. For high-end embedded processors, we add the speed up coming from wider SIMD instructions.","PeriodicalId":393875,"journal":{"name":"Seventh International Workshop on Computer Architecture for Machine Perception (CAMP'05)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2005-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"16-bit floating point instructions for embedded multimedia applications\",\"authors\":\"L. Lacassagne, D. Etiemble, S. A. O. Kablia\",\"doi\":\"10.1109/CAMP.2005.1\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have simulated the implementation of 16-bit floating point instructions on a Pentium4 and PowerPC G4 and G5 to evaluate the performance impact of these instructions in embedded processors for graphics and multimedia applications. Both accuracy of the computations and the execution time have been considered. For low-end embedded processors, the 16-bit FP instructions deliver a larger dynamic range than 16-bit integer with the same memory footprint. For high-end embedded processors, we add the speed up coming from wider SIMD instructions.\",\"PeriodicalId\":393875,\"journal\":{\"name\":\"Seventh International Workshop on Computer Architecture for Machine Perception (CAMP'05)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-07-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Seventh International Workshop on Computer Architecture for Machine Perception (CAMP'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CAMP.2005.1\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Seventh International Workshop on Computer Architecture for Machine Perception (CAMP'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CAMP.2005.1","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
16-bit floating point instructions for embedded multimedia applications
We have simulated the implementation of 16-bit floating point instructions on a Pentium4 and PowerPC G4 and G5 to evaluate the performance impact of these instructions in embedded processors for graphics and multimedia applications. Both accuracy of the computations and the execution time have been considered. For low-end embedded processors, the 16-bit FP instructions deliver a larger dynamic range than 16-bit integer with the same memory footprint. For high-end embedded processors, we add the speed up coming from wider SIMD instructions.
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