An efficient FPGA architecture for hardware realization of hexagonal based motion estimation algorithm

Motion Estimation (ME) is the most critical and complex part of any video codec system. The different algorithms and their architectures are proposed for ME process. In this paper, we have proposed an efficient architecture for Hexagon Based Search (HexBS) algorithm and implemented on XC4VSX25 Virtex4 FPGA. Simulation results show that the proposed architecture is capable of calculating the Motion Vectors (MVs) of 1280×720 High Definition (HD) videos with the best case throughput of 70 frames/sec. Moreover, the power and frequency requirements are 215mW and 127.27 MHz respectively for the proposed architecture with minimum hardware resources. Hence the proposed architecture is suitable for the real-time HD video applications.