{"title":"并行架构:数据流系统的缓存存储器","authors":"A. Hurson, K. Kavi, B. Shirazi, Ben Lee","doi":"10.1109/88.544436","DOIUrl":null,"url":null,"abstract":"Cache memory — so effective in traditional control-flow architecture — has the potential to enhance dataflow system performance as well. The authors explore the recent trend in combining dataflow and control-flow processing, which offers new alternatives in computer architecture design, and analyze cache memory's application to the dataflow environment.","PeriodicalId":325213,"journal":{"name":"IEEE Parallel & Distributed Technology: Systems & Applications","volume":"6 4","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Parallel architectures: Cache memories for dataflow systems\",\"authors\":\"A. Hurson, K. Kavi, B. Shirazi, Ben Lee\",\"doi\":\"10.1109/88.544436\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Cache memory — so effective in traditional control-flow architecture — has the potential to enhance dataflow system performance as well. The authors explore the recent trend in combining dataflow and control-flow processing, which offers new alternatives in computer architecture design, and analyze cache memory's application to the dataflow environment.\",\"PeriodicalId\":325213,\"journal\":{\"name\":\"IEEE Parallel & Distributed Technology: Systems & Applications\",\"volume\":\"6 4\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-01-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Parallel & Distributed Technology: Systems & Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/88.544436\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Parallel & Distributed Technology: Systems & Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/88.544436","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Parallel architectures: Cache memories for dataflow systems
Cache memory — so effective in traditional control-flow architecture — has the potential to enhance dataflow system performance as well. The authors explore the recent trend in combining dataflow and control-flow processing, which offers new alternatives in computer architecture design, and analyze cache memory's application to the dataflow environment.
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