Statistical characterization of chip power behavior at post-fabrication stage

Power/temperature constraints are among the most important design considerations for today's high performance processors. Many dynamic power or thermal management (DPM/DTM) techniques have been proposed to maintain reliable chip operation and meet power constraints. These techniques rely on runtime estimation schemes that can report accurate power and temperature status of the chip during its operation. However many such estimation schemes require prior knowledge of the statistical system power behavior to generate accurate results. In this paper we discuss the problem of extracting the statistical power characteristics of a chip at post-fabrication stage using real workload information. We first model the statistical power characteristics of a chip as a mixture of multiple Gaussian distributions. Each of these distributions essentially captures the behavior of a cluster of similar applications. We then develop an Expectation-Maximization algorithm for learning the parameters of this mixture Gaussian model. The experimental results are compared against the actual power characteristics of the chip simulated using SPEC benchmarks and are shown to be within 97% accuracy range. We also demonstrate how the statistical model learned using our approach can be exploited in a popular Kalman filter framework for accurate runtime temperature estimation.