{"title":"采用动态可重构架构的硬件加速器实现","authors":"Takashi Yoshikawa, Yutaka Yamada, S. Asano","doi":"10.1109/HOTCHIPS.2006.7477752","DOIUrl":null,"url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on the implementation of hardware accelerator using dynamically reconfigurable architecture. Some of the specific topics discussed include: an overview of the reconfigurable architecture; and application example using the H.264 decoding program; performance evaluation of hardware accelerator technologies; and new areas of technological development.","PeriodicalId":302249,"journal":{"name":"2006 IEEE Hot Chips 18 Symposium (HCS)","volume":"235 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An implementation of hardware accelerator using dynamically reconfigurable architecture\",\"authors\":\"Takashi Yoshikawa, Yutaka Yamada, S. Asano\",\"doi\":\"10.1109/HOTCHIPS.2006.7477752\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article consists of a collection of slides from the author's conference presentation on the implementation of hardware accelerator using dynamically reconfigurable architecture. Some of the specific topics discussed include: an overview of the reconfigurable architecture; and application example using the H.264 decoding program; performance evaluation of hardware accelerator technologies; and new areas of technological development.\",\"PeriodicalId\":302249,\"journal\":{\"name\":\"2006 IEEE Hot Chips 18 Symposium (HCS)\",\"volume\":\"235 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Hot Chips 18 Symposium (HCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HOTCHIPS.2006.7477752\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Hot Chips 18 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2006.7477752","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An implementation of hardware accelerator using dynamically reconfigurable architecture
This article consists of a collection of slides from the author's conference presentation on the implementation of hardware accelerator using dynamically reconfigurable architecture. Some of the specific topics discussed include: an overview of the reconfigurable architecture; and application example using the H.264 decoding program; performance evaluation of hardware accelerator technologies; and new areas of technological development.
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