{"title":"可测试的SIMD图形引擎VLSI电路设计","authors":"D. Pok, C.-i.H. Chen","doi":"10.1109/ASIC.1997.616981","DOIUrl":null,"url":null,"abstract":"In every computer graphics system, there is some interaction between a special memory called a frame buffer and a computation engine. It is the architecture between these two that determines how fast, flexible, and expensive the graphics subsystem is. In this paper, we present the testability analysis and chip testing of Enhanced Memory Chip (EMC) using the scan-BIST (built-in self-test) partial scan scenario. EMC is a multi-million transistors graphics computation engine produced by WL/AASE, WPAFB in VHDL formats and is fabricated using 0.5 /spl mu/m CMOS technology. Fundamentally, it is memory that is enhanced with tightly-coupled computational logic on the same chip. The logic is arranged in a single instruction, multiple data architecture that can efficiently perform the linear expression evaluation that is common in the lowest level graphic rasterization. The fault simulation shows that partial scan scenario is feasible for EMC and generates scan-BIST high fault coverage and low overhead.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Testable VLSI circuit design of SIMD graphics engine\",\"authors\":\"D. Pok, C.-i.H. Chen\",\"doi\":\"10.1109/ASIC.1997.616981\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In every computer graphics system, there is some interaction between a special memory called a frame buffer and a computation engine. It is the architecture between these two that determines how fast, flexible, and expensive the graphics subsystem is. In this paper, we present the testability analysis and chip testing of Enhanced Memory Chip (EMC) using the scan-BIST (built-in self-test) partial scan scenario. EMC is a multi-million transistors graphics computation engine produced by WL/AASE, WPAFB in VHDL formats and is fabricated using 0.5 /spl mu/m CMOS technology. Fundamentally, it is memory that is enhanced with tightly-coupled computational logic on the same chip. The logic is arranged in a single instruction, multiple data architecture that can efficiently perform the linear expression evaluation that is common in the lowest level graphic rasterization. The fault simulation shows that partial scan scenario is feasible for EMC and generates scan-BIST high fault coverage and low overhead.\",\"PeriodicalId\":300310,\"journal\":{\"name\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1997.616981\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.616981","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Testable VLSI circuit design of SIMD graphics engine
In every computer graphics system, there is some interaction between a special memory called a frame buffer and a computation engine. It is the architecture between these two that determines how fast, flexible, and expensive the graphics subsystem is. In this paper, we present the testability analysis and chip testing of Enhanced Memory Chip (EMC) using the scan-BIST (built-in self-test) partial scan scenario. EMC is a multi-million transistors graphics computation engine produced by WL/AASE, WPAFB in VHDL formats and is fabricated using 0.5 /spl mu/m CMOS technology. Fundamentally, it is memory that is enhanced with tightly-coupled computational logic on the same chip. The logic is arranged in a single instruction, multiple data architecture that can efficiently perform the linear expression evaluation that is common in the lowest level graphic rasterization. The fault simulation shows that partial scan scenario is feasible for EMC and generates scan-BIST high fault coverage and low overhead.