{"title":"使用冗余位表示的重新编码和非重新编码的三位有符号数字乘法器设计","authors":"A. Cherri, M. S. Alam","doi":"10.1109/NAECON.1998.710183","DOIUrl":null,"url":null,"abstract":"Recently, highly-efficient two-step recoded and one-step nonrecoded trinary signed-digit (TSD) carry-free adder/subtracter has been presented based on redundant bit representation (RBR) for the operands digits where it has been shown that only 24 (30) minterms are needed to implement the two-step recoded TSD (the one-step nonrecoded) addition for any operand length. In this paper, we present four different multiplication designs based on our proposed recoded and nonrecoded TSD adders. Our multiplication designs require a small number of reduced minterms to generate the multiplication partial products.","PeriodicalId":202280,"journal":{"name":"Proceedings of the IEEE 1998 National Aerospace and Electronics Conference. NAECON 1998. Celebrating 50 Years (Cat. No.98CH36185)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Recoded and nonrecoded trinary signed-digit multipliers designs using redundant bit representations\",\"authors\":\"A. Cherri, M. S. Alam\",\"doi\":\"10.1109/NAECON.1998.710183\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recently, highly-efficient two-step recoded and one-step nonrecoded trinary signed-digit (TSD) carry-free adder/subtracter has been presented based on redundant bit representation (RBR) for the operands digits where it has been shown that only 24 (30) minterms are needed to implement the two-step recoded TSD (the one-step nonrecoded) addition for any operand length. In this paper, we present four different multiplication designs based on our proposed recoded and nonrecoded TSD adders. Our multiplication designs require a small number of reduced minterms to generate the multiplication partial products.\",\"PeriodicalId\":202280,\"journal\":{\"name\":\"Proceedings of the IEEE 1998 National Aerospace and Electronics Conference. NAECON 1998. Celebrating 50 Years (Cat. No.98CH36185)\",\"volume\":\"53 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-07-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 1998 National Aerospace and Electronics Conference. NAECON 1998. Celebrating 50 Years (Cat. No.98CH36185)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NAECON.1998.710183\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 1998 National Aerospace and Electronics Conference. NAECON 1998. Celebrating 50 Years (Cat. No.98CH36185)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAECON.1998.710183","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Recoded and nonrecoded trinary signed-digit multipliers designs using redundant bit representations
Recently, highly-efficient two-step recoded and one-step nonrecoded trinary signed-digit (TSD) carry-free adder/subtracter has been presented based on redundant bit representation (RBR) for the operands digits where it has been shown that only 24 (30) minterms are needed to implement the two-step recoded TSD (the one-step nonrecoded) addition for any operand length. In this paper, we present four different multiplication designs based on our proposed recoded and nonrecoded TSD adders. Our multiplication designs require a small number of reduced minterms to generate the multiplication partial products.
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