{"title":"利用片上DRAM探索3D系统的性能、功耗和温度特性","authors":"Jie Meng, Daniel Rossell, A. Coskun","doi":"10.1109/IGCC.2011.6008579","DOIUrl":null,"url":null,"abstract":"3D integration enables stacking DRAM layers on processor cores within the same chip. On-chip memory has the potential to dramatically improve performance due to lower memory access latency and higher bandwidth. Higher core performance increases power density, requiring a thorough evaluation of the tradeoff between performance and temperature. This paper presents a comprehensive framework for exploring the power, performance, and temperature characteristics of 3D systems with on-chip DRAM. Utilizing this framework, we quantify the performance improvement as well as the power and thermal profiles of parallel workloads running on a 16-core 3D system with on-chip DRAM. The 3D system improves application performance by 72.6% on average in comparison to an equivalent 2D chip with off-chip memory. Power consumption per core increases by up to 32.7%. The increase in peak chip temperature, however, is limited to 1.5°C as the lower power DRAM layers share the heat of the hotter cores. Experimental results show that while DRAM stacking is a promising technique for high-end systems, efficient thermal management strategies are needed in embedded systems with cost or space restrictions to compensate for the lack of efficient cooling.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Exploring performance, power, and temperature characteristics of 3D systems with on-chip DRAM\",\"authors\":\"Jie Meng, Daniel Rossell, A. Coskun\",\"doi\":\"10.1109/IGCC.2011.6008579\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"3D integration enables stacking DRAM layers on processor cores within the same chip. On-chip memory has the potential to dramatically improve performance due to lower memory access latency and higher bandwidth. Higher core performance increases power density, requiring a thorough evaluation of the tradeoff between performance and temperature. This paper presents a comprehensive framework for exploring the power, performance, and temperature characteristics of 3D systems with on-chip DRAM. Utilizing this framework, we quantify the performance improvement as well as the power and thermal profiles of parallel workloads running on a 16-core 3D system with on-chip DRAM. The 3D system improves application performance by 72.6% on average in comparison to an equivalent 2D chip with off-chip memory. Power consumption per core increases by up to 32.7%. The increase in peak chip temperature, however, is limited to 1.5°C as the lower power DRAM layers share the heat of the hotter cores. Experimental results show that while DRAM stacking is a promising technique for high-end systems, efficient thermal management strategies are needed in embedded systems with cost or space restrictions to compensate for the lack of efficient cooling.\",\"PeriodicalId\":306876,\"journal\":{\"name\":\"2011 International Green Computing Conference and Workshops\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-07-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 International Green Computing Conference and Workshops\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IGCC.2011.6008579\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Green Computing Conference and Workshops","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IGCC.2011.6008579","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Exploring performance, power, and temperature characteristics of 3D systems with on-chip DRAM
3D integration enables stacking DRAM layers on processor cores within the same chip. On-chip memory has the potential to dramatically improve performance due to lower memory access latency and higher bandwidth. Higher core performance increases power density, requiring a thorough evaluation of the tradeoff between performance and temperature. This paper presents a comprehensive framework for exploring the power, performance, and temperature characteristics of 3D systems with on-chip DRAM. Utilizing this framework, we quantify the performance improvement as well as the power and thermal profiles of parallel workloads running on a 16-core 3D system with on-chip DRAM. The 3D system improves application performance by 72.6% on average in comparison to an equivalent 2D chip with off-chip memory. Power consumption per core increases by up to 32.7%. The increase in peak chip temperature, however, is limited to 1.5°C as the lower power DRAM layers share the heat of the hotter cores. Experimental results show that while DRAM stacking is a promising technique for high-end systems, efficient thermal management strategies are needed in embedded systems with cost or space restrictions to compensate for the lack of efficient cooling.