准循环LDPC码的区域高效存储器访问体系结构的VLSI设计

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI:10.1109/SOCC.2011.6085108

Ming-Der Shieh, Shih-Hao Fang, Shing-Chung Tang, Der-Wei Yang

{"title":"准循环LDPC码的区域高效存储器访问体系结构的VLSI设计","authors":"Ming-Der Shieh, Shih-Hao Fang, Shing-Chung Tang, Der-Wei Yang","doi":"10.1109/SOCC.2011.6085108","DOIUrl":null,"url":null,"abstract":"This paper proposes an area-efficient memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. An efficient algorithm is also presented to handle the additional delay elements. The proposed LDPC decoder has the lowest area complexity among related studies.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes\",\"authors\":\"Ming-Der Shieh, Shih-Hao Fang, Shing-Chung Tang, Der-Wei Yang\",\"doi\":\"10.1109/SOCC.2011.6085108\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes an area-efficient memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. An efficient algorithm is also presented to handle the additional delay elements. The proposed LDPC decoder has the lowest area complexity among related studies.\",\"PeriodicalId\":365422,\"journal\":{\"name\":\"2011 IEEE International SOC Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2011.6085108\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085108","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文提出了一种区域高效的内存访问架构，该架构将小内存块合并到内存组中，以减轻外设在小内存块中的影响。提出了一种有效的算法来处理附加的延迟元素。本文提出的LDPC解码器在相关研究中具有最低的区域复杂度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes

This paper proposes an area-efficient memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. An efficient algorithm is also presented to handle the additional delay elements. The proposed LDPC decoder has the lowest area complexity among related studies.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2011 IEEE International SOC Conference

自引率

0.00%

发文量

期刊最新文献

Keynote speaker An analytical model to estimate PCM failure probability due to process variations A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control “Manufacturing test of systems-on-a-chip (SoCs)” A silicon core for an acoustic archival tag