WiBro系统UDCM的FPGA设计与实现

Kyongkuk Cho, Kyungmin Lee, D. Yoon, Wooju Lee, S. K. Park
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引用次数: 0

摘要

在本文中,我们实现了WiBro基站设备RAS(无线接入站)的UDCM(上下转换模块)。它在信道卡和无线电设备(REs)之间执行数字中频信号处理。UDCM嵌入到RAS的数字光接口单元中。将频率转换为10mhz或基带是主要功能。它对下行链路(DL) /上行链路(UL)的信道带宽内的杂散进行过滤。为了支持与其他芯片或外设的通信,我们设计了接口模块和控制器。由于UDCM在Virtex5系列上进行了优化,可以节省专用FPGA资源,降低开发成本。其功能是使用RTL(寄存器传输级别)上的模拟工具对预定义的测试向量进行验证的。设置好接口信号的时序约束并进行时序校验后,UDCM下载到主机。最后,该数字单元连接到通道卡和REs,通过捕获I/Q,同步信号来确保其参考仿真结果的预期性能。
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FPGA Design and Implementation of UDCM for the WiBro System
In this paper, we implement the UDCM (up down conversion module) for the WiBro base station equipment RAS (radio access station). It performs the digital IF (intermediate frequency) signal processing between a channel card and the radio equipments (REs). The UDCM embed on digital optic interface unit of RAS. Converting the frequency into 10 MHz or baseband is the main function. It filters the spurious within channel bandwidth for downlink (DL) /uplink (UL). Also to support the communication with the other chips or peripherals, we design the interface modules and controller. As the UDCM is optimized on the Virtex5 families, it can save the dedicated FPGA resources and lowers the development costs. Its functionality is verified using simulation tools on the RTL (register transfer level) for the predefined test vector. After setting the timing constraints for the interface signals and timing verification, the UDCM downloaded into main unit. Finally, this digital unit is connected to a channel card and REs to ensure the expected performance for its reference simulation results by capturing I/Q, synchronization signals.
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