Clock distribution network design for single phase energy recovery circuits

Background/Objective: Energy recovery is one of the most promising methods for low power design methodologies. The main idea behind the energy recovery circuits is the use of a slowly rising and slowly falling AC power supply i.e., sinusoidal or trapezoidal clock signal. Hence, it is essential to design low power clocking schemes for such energy recovery circuits. This paper presents an efficient clocking scheme for the energy recovery circuits. Methods/Statistical Analysis: The single phase sinusoidal clock signal which is used to operate the energy recovery circuits is generated from the 2N2P resonant clock generator. The sinusoidal clock signal is routed to the energy recovery circuits through the H-tree clock distribution network. Findings: Single phase energy recovery circuit, namely, the Glitch free and Cascadable Adiabatic Logic (GFCAL) is used to validate the clock network design. 16 inverters are cascaded and connected to the output nodes of the clock tree, and the cascaded chain is driven by the clock signal. Conclusion/Improvement: The simulation results show that the 16-bit adiabatic inverter chain operated at 2GHz incur a power consumption of 184.1 μWatts and the conventional CMOS inverter chain of 16-bit operated at the same frequency incurs power dissipation of 190.2μWatts. All the simulations have been carried out using the industry standard Cadence® Virtuoso tool using 180nm technology library files.