基于3D技术的异构树FPGA设计与优化

V. Pangracious, Z. Marrakchi, H. Mehrez
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引用次数: 0

摘要

CMOS技术的扩展极大地提高了现场可编程门阵列(fpga)的整体性能和密度。然而,当考虑速度、面积和功耗等性能指标时,与专用集成电路(asic)相比,fpga的差距通常非常大,这主要是由于可编程互连开销。我们提出了一种三维(3D)设计方法,使用水平设计划分来垂直堆叠基于树的多层FPGA架构的异构FPGA设计。我们描述了3D设计和优化方法,以提高速度,互连面积和功耗使用Tezzaron的3D堆叠技术。
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Design and optimization of heterogeneous tree-based FPGA using 3D technology
The CMOS technology scaling has greatly improved the overall performance and density of Field Programmable Gate Arrays (FPGAs). However, when looking at the performance metrics such as speed, area and power consumption, the gap is generally very wide for FPGAs compared to application specific integrated circuits (ASICs) mainly due to the programmable interconnect overhead. We propose a 3-dimensional (3D) design methodology using horizontal design partitioning to vertically stack heterogeneous FPGA designs based on a Tree-based multilevel FPGA architecture. We describe the 3D design and optimization methodology to improve speed, interconnect area and power consumption using Tezzaron's 3D stacking technology.
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