基于 MOS 的温度和工艺不变基准电流发生电路,可实现 1V 以下电压运行

Stephen Tang, S. Narendra, V. De
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引用次数: 22

摘要

在采用 150 纳米逻辑工艺技术实现的原型芯片上进行的测量验证了两个 1V 以下 MOS 基准电流发生器电路的理论,并表明在极端工艺和温度条件下,电流变化可减少 /spl sim/2/spl times/。
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Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation
Measurements on a prototype chip, implemented in a 150 nm logic process technology, validate the theories for two sub-1V MOS reference current generator circuits and show that /spl sim/2/spl times/ reduction in current variation is achievable across extremes of both process and temperature.
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Voltage scheduling under unpredictabilities: a risk management paradigm [logic design] Uncertainty-based scheduling: energy-efficient ordering for tasks with variable execution time [processor scheduling] Level conversion for dual-supply systems [low power logic IC design] A selective filter-bank TLB system [embedded processor MMU for low power] A semi-custom voltage-island technique and its application to high-speed serial links [CMOS active power reduction]
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