{"title":"基于 MOS 的温度和工艺不变基准电流发生电路,可实现 1V 以下电压运行","authors":"Stephen Tang, S. Narendra, V. De","doi":"10.1109/LPE.2003.1231862","DOIUrl":null,"url":null,"abstract":"Measurements on a prototype chip, implemented in a 150 nm logic process technology, validate the theories for two sub-1V MOS reference current generator circuits and show that /spl sim/2/spl times/ reduction in current variation is achievable across extremes of both process and temperature.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation\",\"authors\":\"Stephen Tang, S. Narendra, V. De\",\"doi\":\"10.1109/LPE.2003.1231862\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Measurements on a prototype chip, implemented in a 150 nm logic process technology, validate the theories for two sub-1V MOS reference current generator circuits and show that /spl sim/2/spl times/ reduction in current variation is achievable across extremes of both process and temperature.\",\"PeriodicalId\":355883,\"journal\":{\"name\":\"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-08-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LPE.2003.1231862\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LPE.2003.1231862","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 22
摘要
在采用 150 纳米逻辑工艺技术实现的原型芯片上进行的测量验证了两个 1V 以下 MOS 基准电流发生器电路的理论,并表明在极端工艺和温度条件下,电流变化可减少 /spl sim/2/spl times/。
Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation
Measurements on a prototype chip, implemented in a 150 nm logic process technology, validate the theories for two sub-1V MOS reference current generator circuits and show that /spl sim/2/spl times/ reduction in current variation is achievable across extremes of both process and temperature.