ADAM:加速FPGA开发的自动化设计分析和合并

Ho-Cheung Ng, Shuanglong Liu, W. Luk
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引用次数: 9

摘要

ADAM是一种将多个FPGA设计合并到单个硬件设计中的方法,可以用单个任务代替多个放置和路由任务,从而加快设计的功能评估,特别是在开发过程中。ADAM有三个关键要素。首先,提出了一种具有线性时间复杂度的近似最大公子图检测算法,使合并设计中的资源共享最大化。其次,为Verilog设计的数据流图实现这种常见子图检测算法的原型工具;该工具还将生成适当的控制电路,以便在运行时选择原始设计。第三,对编译时间和相似度进行综合分析,以确定所提出方法的优化用户参数。实验结果表明,当每个设计与其他设计相似度达到95%时,ADAM可以将编译时间减少约5倍,在二项滤波器的情况下,编译时间从1小时减少到10分钟。
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ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development
This paper introduces ADAM, an approach for merging multiple FPGA designs into a single hardware design, so that multiple place-and-route tasks can be replaced by a single task to speed up functional evaluation of designs, especially during the development process. ADAM has three key elements. First, a novel approximate maximum common subgraph detection algorithm with linear time complexity to maximize sharing of resources in the merged design. Second, a prototype tool implementing this common subgraph detection algorithm for dataflow graphs derived from Verilog designs; this tool would also generate the appropriate control circuits to enable selection of the original designs at runtime. Third, a comprehensive analysis of compilation time versus degree of similarity to identify the optimized user parameters for the proposed approach. Experimental results show that ADAM can reduce compilation time by around 5 times when each design is 95% similar to the others, and the compilation time is reduced from 1 hour to 10 minutes in the case of binomial filters.
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