低β 650兆赫五腔的中温炉烘烤

G. Wu, S. Posen, V. Chouhan, A. Netepenko, F. Furuta, G. Eremeev, K. McGee, H. Park, S. Chandrasekaran, J. Ozelis, A. Murthy
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引用次数: 2

摘要

在特高压炉中对低β 650 MHz空腔进行了中温烘烤。系统地研究了腔体表面电阻的组成,残余和BCS,包括分析了由于捕获磁通引起的表面电阻。在2k下,腔体在17 MV/m时的平均表面电阻为4.5纳欧姆,满足PIP-II规格,裕度为40%。该结果为PIP-II项目优化低温模块应用的空腔加工配方提供了有益的信息。将实验结果与1.3 GHz腔体进行了比较。
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Medium Temperature Furnace Baking of Low-beta 650 MHz Five-cell Cavities
Medium Temperature baking of low beta 650 MHz cavities was conducted in a UHV furnace. A systematic study of cavity surface resistance components, residual and BCS, was conducted, including analyzing surface resistance due to trapped magnetic flux. Cavities showed an average 4.5 nano-ohm surface resistance at 17 MV/m under 2 K, which meets PIP-II specifications with a 40% margin. The results provided helpful information for the PIP-II project to optimize the cavity processing recipe for cryomodule application. The results were compared to the 1.3 GHz cavity that received a similar furnace baking.
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