{"title":"Firsynth:用于高级FIR滤波器合成的CAD工具","authors":"O. Alpago, Federico G. Zacchigna, A. Lutenberg","doi":"10.1109/SASE-CASE.2014.6914460","DOIUrl":null,"url":null,"abstract":"A software tool for high-level synthesis of Finite Impulse Response (FIR) filters is presented. The tool is based on Canonic Signed Digit (CSD) coding for filter coefficients and Nonrecursive Signed Common Subexpression Elimination algorithm (NR-SCSE) for logic operators (adders and subtractors) mini-mization. By means of this tool a fully-synthesizable HDL code can be generated which is suitable for Field Programmable Gates Arrays (FPGA) as well as for Application Specific Integrated Circuits (ASIC). In this paper all the algorithms implemented are described. Logic operators (LOs) are based on ripple carry structures (RCS) in order to save area and simplify routing. The source code was developed in C programming language and can be used under GNU General Public License (GNU-GPL).","PeriodicalId":202437,"journal":{"name":"2014 Fifth Argentine Symposium and Conference on Embedded Systems SASE/CASE 2014","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Firsynth: A CAD tool for high-level FIR filter synthesis\",\"authors\":\"O. Alpago, Federico G. Zacchigna, A. Lutenberg\",\"doi\":\"10.1109/SASE-CASE.2014.6914460\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A software tool for high-level synthesis of Finite Impulse Response (FIR) filters is presented. The tool is based on Canonic Signed Digit (CSD) coding for filter coefficients and Nonrecursive Signed Common Subexpression Elimination algorithm (NR-SCSE) for logic operators (adders and subtractors) mini-mization. By means of this tool a fully-synthesizable HDL code can be generated which is suitable for Field Programmable Gates Arrays (FPGA) as well as for Application Specific Integrated Circuits (ASIC). In this paper all the algorithms implemented are described. Logic operators (LOs) are based on ripple carry structures (RCS) in order to save area and simplify routing. The source code was developed in C programming language and can be used under GNU General Public License (GNU-GPL).\",\"PeriodicalId\":202437,\"journal\":{\"name\":\"2014 Fifth Argentine Symposium and Conference on Embedded Systems SASE/CASE 2014\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 Fifth Argentine Symposium and Conference on Embedded Systems SASE/CASE 2014\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SASE-CASE.2014.6914460\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Fifth Argentine Symposium and Conference on Embedded Systems SASE/CASE 2014","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SASE-CASE.2014.6914460","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Firsynth: A CAD tool for high-level FIR filter synthesis
A software tool for high-level synthesis of Finite Impulse Response (FIR) filters is presented. The tool is based on Canonic Signed Digit (CSD) coding for filter coefficients and Nonrecursive Signed Common Subexpression Elimination algorithm (NR-SCSE) for logic operators (adders and subtractors) mini-mization. By means of this tool a fully-synthesizable HDL code can be generated which is suitable for Field Programmable Gates Arrays (FPGA) as well as for Application Specific Integrated Circuits (ASIC). In this paper all the algorithms implemented are described. Logic operators (LOs) are based on ripple carry structures (RCS) in order to save area and simplify routing. The source code was developed in C programming language and can be used under GNU General Public License (GNU-GPL).
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