Hardware Implementation of Pseudo-Random Numbers on CPLD

The article proposes a hardware solution for generating pseudo-random numbers. The VHDL development environment was chosen as a platform for implementation of CPLDs, because this programming environment satisfies all technological advancements in integrated circuits, where you can easily create digital designs and transfer them to circuits manually or automatically. The main purpose of the work is to present algorithms with execution on CPLDs that will allow creating a fast, efficient and inexpensive pseudo-random number generator. The resulting configurable generator can be used in a wide range of applications where the use of various pseudo-random sequences is required, for example, in implementation built-in self-testing for digital devices. The flowchart and an example of generation are given