Efficient implementation of tap delay line filter using high speed Digital Signal Processor

An efficient implementation of the linear Finite Impulse Response (FIR) Filter has been performed over the Texas Instrument (TI) TMS320C6416 fixed point Digital Signal Processor (DSP) platform. The implementation fully exploits the pipelined architecture of the processor along with the circular buffering to gain the speed factor of 7 times than the reference approach hence making this more suitable for high speed real-time signal processing applications involving tap delay line (TDL) model.