FPGA implementation and power efficient CORDIC based ADPLL for signal processing and application

Most of the electronic circuit components do not receive the clock at same time due to various factors involved in circuitry. Phase locked loop is a precision and familiar circuit for high frequency and high accuracy application with very short interlocking time. This paper presents All Digital Phase Locked Loop (ADPLL) and has been analysed for the required applications on the basis of its cost, power consumption and speed of operation for phase locked loop. In the given ADPLL system phase detection system has been realized by generating analytic signal using Hilbert transform and then computing the instantaneous phase using CORDIC algorithm. The loop filter of the ADPLL has been designed using a low pass filter and is used to discard the higher order harmonics. The proposed architecture is implemented using VHDL code and is synthesized using Xilinx ISE 9.2 software. To validate its functionality, verification and simulation is done by using the Modelsim SE 6.2C. The ADPLL is planned for 100 MHz central frequency. The work in this paper mainly deals with the power efficiency of ADPLL.