An Efficient Implementation of Decimal Adder Using Parallel Prefix Addition

The majority applications such as traffic light control, Elevator, Valet car parking system uses LED displays to show the numbers. Sequential counters are used in those applications in which it represents the numbers in four bit binary coded decimal (BCD) form. In byte oriented systems BCD is a decimal representation of a number directly coded in binary digit by digit. Applications of addition in BCD found in many applications which uses decimal data. This paper proposes an efficient implementation of Binary Coded Decimal Adder (BCDA) using parallel prefix addition which consumes very less power, operating with greater speed and also occupies less area. The proposed adder architecture is simulated using Xilinx 14.2 and power, area and delay results are carried out using cadence software. The proposed adder results in very less power consumption, operating with greater speed and also occupies less area.