J. Kudoh, Toshiro Takahashi, Yukio Umada, M. Kimura, Shigeru Yamamoto, Y. Ito
{"title":"带有动态终止GTL I/O电路的CMOS门阵列","authors":"J. Kudoh, Toshiro Takahashi, Yukio Umada, M. Kimura, Shigeru Yamamoto, Y. Ito","doi":"10.1109/ICCD.1995.528786","DOIUrl":null,"url":null,"abstract":"A 530 kG gate array with novel GTL I/O circuits has been developed using 0.5 /spl mu/m CMOS triple-metal-layer process technology. The I/O circuit of a push-pull output driver and a dynamic termination receiver can transmit 250 Mb/s data through a long stub line which is connected to a terminated bus line. IDDQ testability is designed for the differential receiver without any delay time overheads.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A CMOS gate array with dynamic-termination GTL I/O circuits\",\"authors\":\"J. Kudoh, Toshiro Takahashi, Yukio Umada, M. Kimura, Shigeru Yamamoto, Y. Ito\",\"doi\":\"10.1109/ICCD.1995.528786\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 530 kG gate array with novel GTL I/O circuits has been developed using 0.5 /spl mu/m CMOS triple-metal-layer process technology. The I/O circuit of a push-pull output driver and a dynamic termination receiver can transmit 250 Mb/s data through a long stub line which is connected to a terminated bus line. IDDQ testability is designed for the differential receiver without any delay time overheads.\",\"PeriodicalId\":281907,\"journal\":{\"name\":\"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.1995.528786\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1995.528786","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
摘要
采用0.5 /spl μ m CMOS三金属层工艺技术,研制出了具有新型GTL I/O电路的530 kG栅极阵列。推挽输出驱动器和动态终端接收器的I/O电路可以通过连接到终端总线的长stub线传输250 Mb/s的数据。差分接收机的IDDQ可测试性设计没有任何延迟时间开销。
A CMOS gate array with dynamic-termination GTL I/O circuits
A 530 kG gate array with novel GTL I/O circuits has been developed using 0.5 /spl mu/m CMOS triple-metal-layer process technology. The I/O circuit of a push-pull output driver and a dynamic termination receiver can transmit 250 Mb/s data through a long stub line which is connected to a terminated bus line. IDDQ testability is designed for the differential receiver without any delay time overheads.