Bias dependence of NMOS and PMOS equivalent input circuits for 32–16nm gate length

As CMOS evolves from 32nm down to 16nm technologies, several technological changes suggest we can more efficiently use linear RC approximations to model the input stages of NMOS & PMOS. This improves the non-linearity of input stages of analog circuits such as RF amplifiers and buffers with input signal voltage levels, thus allowing better matching networks. This linearization is also critical when using fast spice in modeling the digital parts of a mixed signal RFICs. For physical gate lengths of 32 – 16nm, smaller gate area results in more pronounced role for overlap capacitance over source/drain (which is independent of voltage). Metal gates have replaced polysilicon, eliminating polysilicon depletion. This makes effective gate capacitance less voltage dependent in inversion. Metal gates have low resistivity, which makes non-quasi static characteristics easier to model and more uniform along the channel width, because of the reduction of the distributed gate resistance effect. Finally, using high dielectric constant (high-k) dielectrics to replace the thin gate oxides resulted in drastic reduction in gate leakage direct tunneling current, which is modeled as parallel conductance with an exponential dependence on applied gate voltage. In this paper, recently reported technology device features are used to update BSIM4 predictive technology models (PTM). The dependence of the NMOS & PMOS input equivalent circuits on applied biasing for 32–16nm gate lengths is simulated using SPICE circuit simulator.