Flexible line speed network packet classification using hybrid on-chip matching circuits

Packet classification is a core feature needed in firewalls, SDN switches, and QoS routers. Current research to accelerate the classification with hardware employing Field-programmable Gate Arrays (FPGAs) created a variety of approaches, with significant differences in terms of hardware resource requirements, memory usage, configuration update time, and power dissipation. However, there is no optimal, universal method for classification at link rate, due to inherent conflicts between large generic circuits with high resource consumption, and optimized circuits with limited versatility. Thus, current implementations have different trade-offs in terms of memory usage, resource requirements, power consumption, and flexibility. As a new approach to tackle this challenge, we present a hybrid concept that combines an highly optimized configuration-specialized and thus energy- and resource-efficient classification circuit with a generic matching circuit whose configuration can be updated quickly. The combined circuit can thus support reasonably fast configuration updates, has a low power dissipation, and can process network packets at link rate.