性能优化的多FPGA分区

Kalapi Roy-Neogi, C. Sechen
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引用次数: 42

摘要

我们解决了将FPGA电路映射到特定目标技术的多个FPGA上的技术分区问题。多FPGA系统(MFS)的物理特性对电路划分算法提出了额外的约束:每个FPGA的容量、时序约束、每个FPGA的I/ o数量以及预先设计的MFS互连模式。现有的仅仅最小化分区分割大小的分区技术无法满足上述挑战。因此,我们提出了一种有效而准确地处理时序规范的线性划分算法。使用特定于多FPGA架构的时序模型来估计分区期间的信号路径延迟。该模型将系统中所有可能的延迟因素与目标技术的多个FPGA芯片相结合。采用了一种新的动态净加权方案,以最大限度地减少每个芯片的引脚数。最后,我们开发了一个基于图的全局引脚分配路由器,它可以处理我们的MFS结构的预路由连接。我们成功地对MCNC赛灵思FPGA基准进行了分区,在所有情况下都产生了100%可路由的高利用率设计。使用我们方法中的性能优化功能,我们已经成功地划分了满足关键路径约束的这些基准,并显著减少了最长路径延迟。最长路径延迟平均减少17%,而总导线长度减少5%。通过验证分区器的时间预测和分区MFS放置和路由后获得的实际延迟,我们证明了性能优化技术的有效性。使用Xilinx映射的MCNC基准测试获得的分区结果令人鼓舞。
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Multiple FPGA Partitioning with Performance Optimization
We address the problem of partitioning a technology mapped FPGA circuit onto multiple FPGAs of a specific target technology. The physical characteristics of the multiple FPGA system (MFS) pose additional constraints to the circuit partitioning algorithms: the capacity of each FPGA, the timing constraints, the number of I/Os per FPGA, and the pre-designed interconnection patterns of the MFS. Existing partitioning techniques which minimize just the cut sizes of partitions fail to satisfy the above challenges. We therefore present a rectilinear partitioning algorithm which efficiently and accurately handles timing specifications. The signal path delays are estimated during partitioning using a timing model specific to a multiple FPGA architecture. The model combines all possible delay factors in a system with multiple FPGA chips of a target technology. A new dynamic net-weighting scheme was incorporated to minimize the number of pin-outs for each chip. Finally, we have developed a graph-based global router for pin assignment which can handle the pre-routed connections of our MFS structure. We successfully partitioned the MCNC Xilinx FPGA benchmarks producing 100% routable designs with high utilization levels in all cases. Using the performance optimization capabilities in our approach we have successfully partitioned these benchmarks satisfying the critical path constraints and achieving a significant reduction in the longest path delay. An average reduction of 17% in the longest path delay was achieved at the cost of 5% in total wire length. We have proved the effectiveness of our performance optimization technique by verifying the timing predictions of our partitioner with the actual delays obtained after placement and routing of a partitioned MFS. Partitioning results obtained with the Xilinx mapped MCNC benchmarks are encouraging.
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